Voltage boosters are integrated in memory devices and other type devices to provide higher voltages than the supply voltage. Higher voltages are necessary, for example, in non-volatile memory devices for erasing and writing data, for enhancing the driving conditions (overdriving) of output power devices and other purposes.
Voltage boosters are also used for generating a boosted clock signal for driving the switches of a charge pump. A boosted clock is necessary for allowing the switches that connect in parallel a pump capacitor with a tank capacitor of a charge pump to remain on as long as both capacitors are at the same voltage.
Voltage boosters use a relatively large capacitance CTot for generating a large voltage. For a multi-stage voltage booster having N stages, the output voltage VOut is given by the following equation:
      V    Out    =                    (                  N          +          1                )            ·              V        dd              -                  N        2            ·                        I          L                          f          ·                      C            Tot                              where Vdd is the supply voltage of the voltage booster, IL is the current to be delivered, and f is the switching frequency of the voltage booster.
To reduce the silicon area occupied by a voltage booster for the same output voltage VOut, it is necessary to reduce its capacitance CTot and to increase the switching frequency of its switches. Voltage boosters used for generating a boosted clock signal for a charge pump are usually called clock-boosters, and this expression will be used below.
A common clock-booster is depicted in FIG. 1. It is substantially composed of two identical sub-circuits each generating a respective boosted phase VOUT1A and VOUT1B. Each sub-circuit has an NMOS transistor controlled by the boosted phase output by the other sub-circuit, and a PMOS transistor controlled by a respective input control phase VIN, {overscore (VIN)}. The voltage drops on the PMOS transistor may surpass the supply voltage Vdd and thus, these transistors should be high-voltage transistors. That is, each high-voltage transistor has a gate oxide of increased thickness and with an increased channel length.
The clock-booster should not be used for frequencies higher than 10 MHz. At higher frequencies, the relatively large parasitic capacitances that affect the high-voltage transistors HV strongly limit performance.
Published U.S. patent application no. 2003/0174010, which is assigned to the assignee of the invention and is incorporated herein by reference in its entirety, discloses an improved clock-booster, as illustrated in FIG. 2. The clock-booster has a reduced silicon area requirement. One of the high-voltage transistors of FIG. 1 is substituted with a low-voltage transistor. The output node is pre-charged with the voltage Vdd, and the output voltage is held before the output node is discharged.
This configuration saves silicon area and reduces current consumption up to a frequency of about 10 MHz. At higher frequencies, it is necessary to have a larger high-voltage MOS transistor P2 for increasing its conductance. In doing so its parasitic capacitance is also inevitably increased, and the advantages compared to the clock-booster of FIG. 1 are jeopardized. Indeed, in the clock-booster of FIG. 1 for 50 MHz the pass-transistor that connects the capacitance C to the output node should have a channel of 400 μm/0.8 μm, while in the clock-booster of FIG. 2 it should have a channel of 1500 μm/0.8 μm.
Low-voltage transistors have a relatively small capacitance, and therefore, are perfectly suited for functioning at a frequency of 50 MHz or above. Therefore, a clock-booster made exclusively with low-voltage transistors would show good performances even at relatively high frequencies. Unfortunately, as discussed above, known clock-boosters rely on the use of a certain number of high-voltage transistors.